FIG. 4 illustrates by way of example a known state of the art microcontroller (hereafter referred to as μCOM). FIG. 4 is an exemplary configuration of a common 8-bit microcontroller. As shown in this figure, the μCOM 1 comprises an external memory unit 2 that stores a program data, and a central processing unit 3 (hereafter referred to as CPU) that reads instructions constituting the program data in a predetermined order and executes the instructions. The external memory unit 2 and the CPU 3 are connected to each other via an address bus BA, a data bus BD, and a control signal line L1.
The program data is constituted by the instructions. As shown in FIG. 5, the instructions may comprise a 1-byte instruction having instruction information part only, a 2-byte instruction having the instruction information part and one operand (i.e., complementary information part in the context of the invention) for execution of the instruction information part, and a 3-byte instruction having the instruction information part and two operands for execution of the instruction information part. The instruction information part and the operand are each configured as an 8-bit data.
As shown in FIG. 4, the external memory unit 2 comprises a plurality of 8-bit data areas each having an address from 0000H to an FFFFH in this order. One instruction information part or one operand is stored in one data area.
The 1-byte instruction is an instruction for which one read operation (of the instruction information part) is required for executing it such as copying data from the A register 33a to the B register 33b in the CPU 3. The 2-byte instruction is an instruction for which two rounds of read operation (of the instruction information part and one operand) is required for executing it such as adding the operand data to data stored in a register of the CPU 3. The 3-byte instruction is an instruction for which three rounds of read operation (of the instruction information part, a first operand, and a second operand) are required for executing it such as reading data from addresses in the external memory unit 2 designated by the two operands.
The CPU 3 comprises a control circuit 31 adapted for instruction analysis and arithmetic processing in accordance with the instruction analysis, an IR register 32, a register set 33, a first LATCHI register 34, a second LATCHI register 35, an address latch 36, and a program counter (hereafter referred to as PC) register 37. These elements are connected to each other via an internal bus Bin. The control circuit 31 controls the overall CPU 3 system, analyses the instruction information parts and executes the instructions. The ER register 32 is a register in which the instruction information part is stored.
The register set 33 comprises an A register 33a, a B register 33b, a C register 33c, a D register 33d, an E register 33e, an F register 33f, an H register 33h, and an L register 33l. These registers are general registers for use in temporarily storing data in the course of arithmetic processing by the control circuit 31.
The first LATCHI register 34 is a register used to store the upper 8 bits residing at the address indicated by the operand, and the second LATCHI register 35 is a register used to store the lower 8 bits residing at the address indicated by the operand. The address latch 36 is a register used to specify the 16-bit address of the external memory unit 2 to be output on the address bus BA.
The PC register 37 is a 16-bit register, content of which is output to the address latch 36, and output via the address bus BA to the external memory unit 2. The address stored in the PC register 37 is incremented each time the CPU 3 reads the instruction information part or the operand. In other words, the CPU 3 reads the instruction information part and the operand on a per address basis. Since the PC register 7 is reset to 0 upon resetting of the CPU 3, the CPU 3 will always start reading starting from the address 0000H of the external memory unit 2.
Next, the operation of the CPU 3 as shown in FIG. 4 is described with reference to FIGS. 6 to 9, in an illustrative case where the 3-byte instructions are stored at the address 0000H to address 0002H in the external memory unit 2.
First, the CPU 3 performs initialization upon being started up. In this initializing process, the control circuit 31 in the CPU 3 resets the PC register 37 to the address 0000H. Next, as shown in FIG. 6, the control circuit 31 outputs the address (address 0000H) stored in the PC register 37 to the address latch 36. Thus, the address 0000H is output to the external memory unit 2 via the address bus BA. Next, the control circuit 31 outputs a read signal via the control signal line L1.
When the read signal is input to the external memory unit 2, the external memory unit 2 outputs data via the data bus BD, the data residing at the address 0000H that has been input via the address bus BA. Since the instruction information part resides at the address 0000H, the instruction information part is output via the data bus BD to the CPU 3. The control circuit 31 in the CPU 3 stores this instruction information part in the IR register 32, the instruction information part having been output via the data bus BD.
Subsequently, as shown in FIG. 7, the control circuit 31 increments the PC register 37 so that the counter results in 0001H. Also, the control circuit 31 decodes the instruction information part stored in the IR register 32, and interprets that this instruction information part is an instruction to read data from the address in the external memory unit 2 specified by two operands and store the read data in the A register 33a. 
It should be noted that there exist several hundreds or more types of instructions, some of which are illustrated by way of example.
Next, the control circuit 31 outputs the address (address 0001H) stored in the PC register 37 to the address latch 36. Thus, the address 0001H is output via the address bus BA to the external memory unit 2. Following this, the control circuit 31 outputs the read signal via the control signal line L1.
When the read signal is input, the external memory unit 2 outputs via the data bus BD the data stored at the address 0001H input via the address bus BA. Since the operand is stored in the address 0001H, the operand will be output to the CPU 3 via the data bus BD. The control circuit 31 stores in the second LATCHI register 35 the lower field at the address indicated by the operand output via the data bus BD.
Subsequently, as shown in FIG. 8, the control circuit 31 increments the PC register 37 by 1 so that the counter results in 0002H. Next, the control circuit 31 outputs the address (address 0002H) stored in the PC register 37 to the address latch 36. Thus, the address 0002H is output to the external memory unit 2 via the address bus BA. Following this, the control circuit 31 outputs the read signal via the control signal line L1.
When the read signal is input, the external memory unit 2 outputs the data stored at the address 0002H input from the address bus BA via the data bus BD. Since the operand is store at the address 0002H, the operand will be output via the data bus BD to the CPU 3. The control circuit 31 in the CPU 3 stores the upper filed in the address indicated by the operand output via data bus BD in the first LATCHI register 34.
Subsequently, the control circuit 31 increments the PC register 37 by 1, so that it results in 0003H as shown in FIG. 9. Next, the control circuit 31 output the address stored at the first and second LATCHI registers 34, 35 to the address latch 36. Thus, the address specified by the two operands is output via the address bus BA to the external memory unit 2. Next, the control circuit 31 outputs the read signal via the control signal line L1.
When the read signal is input, the external memory unit 2 outputs the data residing at the address input by the address bus BA, outputs it via the data bus BD. The control circuit 31 in the CPU 3 stores the data output via the data bus BD, stores it in the A register 33a, and thus the operation for one instruction is completed.
After that, the control circuit 31 outputs the address (0003H address) stored in the PC register 37 to the address latch 36, and reads the next instruction in the IR register 32, decodes it, executes it, and this operation is repeated.
Since the CPU 3 is not capable of directly reading the instruction information part and the operand stored in the external memory unit 2, the CPU 3 needs to store the instruction information part and the operand originally stored in the external memory unit 2 in the internal registers 32, 33a to 33l, 34, and 35 from which data can be directly read by the CPU 3.
Accordingly, the CPU 3 of the μCOM 1 needs to perform instruction-read operation one time for 1-byte instruction, twice for 2-byte instruction, and three times for 3-byte instruction, the instruction-read operation including outputting the address via the address bus BA, outputting the read signal via the control signal line L1, storing the instruction information part or the operand via the data bus BD temporarily in the registers 32, 33a to 33l, 34, and 35 for reading thereof. This implies that reading of the instructions takes much time.
Also, reading and writing of the data by the CPU 3 to and from the external memory unit 2 are performed as described below. Specifically, with regard to reading of data from the external memory unit 2, as described in the foregoing, after the CPU 3 has output the address to be read to the address bus BA, the CPU 3 outputs the read signal. When the read signal is input, the external memory unit 2 outputs the data stored at the address input via the address bus BA, outputs it via the data bus BD. Meanwhile, with regard to w2riting of data in the external memory unit 2, the CPU 3 outputs the address for writing via the address bus BA and outputs the data for writing via the data bus BD, and subsequently outputs the write signal. The external memory unit 2, when the write signal is input, stores the data input from the data bus BD at the address input via the address bus BA.